1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices, and more particularly, to a method of fabricating semiconductor devices including PMOS devices having embedded SiGe (eSiGe).
2. Description of the Related Art
In order to meet the demand of users for low profile electronics, in enhanced Very Large Scale Integration (VLSI) processes, stress engineering has been used to improve performance of devices. One of the effective ways is to utilize embedded SiGe (eSiGe) structures to increase hole mobility in the channel regions of a PMOS device.
In a Sigma-shaped (Σ-shaped) SiGe structure, stress in the channel regions can be effectively increased since the lattice constant of SiGe is larger than that of Si and the distance between source and drain regions is reduced by using the Σ-shaped SiGe structure.
A prior art method of forming a Σ-shaped SiGe structure in a PMOS device is shown in FIGS. 1A to 1D. After forming on a Si substrate a gate medium layer (not shown), gates are disposed on the gate medium layer, and sidewall spacers are formed on both sides of each gate as shown in FIG. 1A. Thereafter, a recess with a substantially rectangular cross section is formed between adjacent gates in the Si substrate by dry etching, as shown in FIG. 1B. For example, the substrate surface can be selected as having a (100) orientation.
Next, as shown in FIG. 1C, the recess is etched using an orientation selective wet etchant, such as an etchant containing Tetramethylammonium hydroxide (TMAH), to expand it into a recess having a Σ-shaped cross section. SiGe is epitaxially grown in the resulting Σ-shaped recess, so as to form SiGe source and drain regions, as shown in FIG. 1D.
After reviewing the prior art methods of forming Σ-shaped SiGe cross section, inventors of the present invention discovered that the conventional methods face problems of difficult epitaxial growth of SiGe and high loading effect.
In an orientation selective wet etching process shown in FIG. 1C, when using an etchant containing TMAH, for example, the etching rate in a <100> orientation is far higher than that in a (111) orientation. Thereby, with respect to a substrate for which its surface has a (100) orientation, it is very difficult to control process conditions to stop the etching before the intersection of (111) crystal planes on opposite sides of the recess (FIG. 1D). Consequently, an orientation selective wet etching tends to result in a recess with a cuspate but not a flat bottom as shown in FIG. 1E. A recess having a cuspate cross-sectional shape may have difficulties in the subsequent epitaxial growth of SiGe and result in defected semiconductor devices.
However, in VLSI fabrication processes, different areas on a substrate may have different device densities. For example, areas to be used for static random access memory (SRAM) may generally have a density higher than that of those areas to be used for logic devices. Due to the loading effect associated with wet etching, the etching in the areas with a lower device density is faster than the etching in the areas with a higher device density. Hence, when the orientation selective wet etching process mentioned above is carried out on a bulk substrate, if etching conditions are tuned on the basis of low density devices, under-etching may occur at high density devices. On the other hand, if etching conditions are tuned on the basis of high density devices, Σ-shaped recesses having cuspate bottoms as shown in FIG. 1E may occur in low density devices.